1. Field of the Invention
This invention relates generally to the field of digital interface design and, more particularly, to communications interface design.
2. Description of the Related Art
Within the past two decades personal computers (PC) have joined television sets, high fidelity stereo equipment, and compact disc players as part of the vast array of electronic devices widely used in both the office and the home. In recent years the electronics marketplace has also seen a proliferation of appliances and personal electronics devices that use solid-state memory, in addition to devices that employ other widely used storage mediums. Some of the more popular devices include video cameras, photo cameras, personal digital assistants and portable music devices, among others. Corresponding to the proliferation of personal computers and associated peripheral devices has been an emphasis on connectivity and networking for transferring data between the personal electronic devices and personal computers, as well as for sharing the data between the personal computers themselves.
In addition to specifications for internal busses, such as the Peripheral Component Interconnect (PCI), various interface standards for connecting computers and external peripherals have also been introduced, each aiming to provide simple connectivity at high speeds. Examples of such standards include the IEEE 1394 standard also referred to as FireWire, and the Universal Serial Bus (USB), both high-speed serial bus protocols. The most widely used networking standard for connecting computers in both Local Area Networks (LANs) and Wide Area Networks (WANs) has been the Ethernet protocol. More specifically, Ethernet is the IEEE 802.3 series standard, based on the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) method that provides a means for two or more computer stations to share a common cabling system. CSM/CD is the basis for Ethernet systems that range from speeds of 1 Mb/s through 1000 Mb/s. Ethernet generally makes efficient use of shared resources, is typically easy to reconfigure and maintain, and provides compatibility across many manufacturers and systems, while keeping the cost low.
Whether transferring data over the PCI bus, or between personal computers, peripheral devices and/or networks over FireWire, USB, or an Ethernet connection, processing of the data usually requires the movement of that data from one location of the host memory to another memory location. Various hardware methods may be used when transferring the data from one location to another. Examples of such methods include Programmed Input/Output (PIO), simple Slave Direct Memory Access (DMA), descriptor-based DMA, and combinations of PIO and DMA. The host memory could be internal to or associated with a processor, while the other location could be another host memory address or a peripheral hardware device attached to the host system also mapped in memory. This type of peripheral device is also referred to as a “Memory” mapped and/or “I/O” mapped device.
Most processors require that objects and variables constituting the data reside at particular offsets in the system's memory. For example, 32-bit processors typically require a 4-byte integer to reside at a memory address that is evenly divisible by 4. This requirement is generally called “memory alignment”. Thus, for example a 4-byte integer can be located at memory address 0x2000 or 0x2004, but not at 0x2002. On many systems, for example 32-bit RISC CPU systems, an attempt to use misaligned data may result in a bus error, which might terminate the program altogether. In case of other systems, for example systems based on certain Intel processors, the use of misaligned data is generally supported but at a substantial performance penalty. There are often times specific memory alignment requirements that need to be met in order for the data to be moved efficiently. This is especially true in the embedded processor application space and associated system architectures, which in order to copy a data buffer from one location in the computer system to another will require software complexities that incur additional time, thus reducing overall system performance.
Memory alignment requirements may need to overcome limitations that include but may not be limited to cache line and/or address alignment. For example, regarding Ethernet data transfers, some network device driver environments send transmit packets to the device driver in nicely aligned single buffers that are both physically and virtually contiguous. In such cases alignment is not an issue. Other network device driver environments however may represent transmit packets as a linked list of buffer fragments of arbitrary length. Each buffer might start and end on an arbitrary byte boundary. Each buffer fragment might be virtually contiguous, containing one or more physical page break or breaks. Transmit packets with large payload data are more likely to contain physical system memory page breaks than smaller ones.
Many data communication controllers require that transmit data be presented to the controller in an aligned fashion. Since the data generally arrives to the driver in unaligned fragments, the driver must typically use the CPU to gather the scattered fragments and re-align the data before writing it to the network interface card (NIC). This process is illustrated in part in FIG. 1, where non-contiguous memory buffers 901 and 902 are not memory aligned on a 32-bit boundary. Buffers 901, and 902 contain data that may have been written into system memory by an operating system running on a processor or microcontroller configured in the system. Portions of the data, shown in boxes 910a through 910d are not part of the data to be transmitted, and may thus typically represent unwanted data for a data communications controller, which is generally configured in the system for transferring data to a remote memory. One example of such a data communications controller might be an Ethernet controller on a NIC for coupling the system to a LAN. The host system software, in conjunction with the data communications driver software (shown as CPU Software 910), may be required to copy the data buffers into a secondary data memory 903 where the data will typically be aligned. The host system software in conjunction with the data communications driver software then typically copies data buffer 903 into the data communications controller memory, as illustrated by buffer 904.
This process may often result in a waste of computing resources. In general, a reduction of data copying in a communications data flow increases throughput and reduces latencies. In addition, as previously mentioned, many processors have alignment restrictions often forcing a CPU to access the data as individual bytes regardless of the size of the CPU's internal registers and/or the width of the data bus. In order to meet memory alignment requirements for embedded systems that typically interface to a local bus other than a PCI bus, the ability to increase performance and flexibility of transferring the data from a processor or associated memory location to another memory or I/O mapped location may gain increased importance.
It should be noted that PCI, where memory misalignment may still be an issue, supports “Bus Master DMA”, which is capable of addressing memory misalignment issues in certain systems. When a Bus Master DMA is used, the host LAN driver or operating system software typically programs the DMA controller to move specific data buffers with specific starting and ending addresses. In many cases, the Bus Master DMA controller can support moving multiple data autonomously via linked list software data structures, with descriptor elements embedded within the software data structures. Each descriptor may describe all of the parameters necessary for moving the data (for example start address, end address, and data length among other fields). The DMA Bus Master controller generally addresses Byte, Word, and Double Word alignment issues by using some form of hardware bus technology. For example, the PCI bus utilizes “Byte Enable” signals to determine system Byte, Word and Double Word accesses.
However, present systems that are not configured as Bus Master systems typically address memory misalignment issues, and handle memory alignment requirements, in software. Software solutions are generally time consuming and lead to a substantial reduction in system performance. For example, in the case of an Ethernet controller, there may be a need for efficient handling of transmit packets and receive packets, reducing the time as well as the required CPU cycles of each data transfer from or to the Ethernet network.
Other corresponding issues related to the prior art will become apparent to one skilled in the art after comparing such prior art with the present invention as described herein.